This Invention relates generally to FPLL (frequency and phase looked loop) circuits and specifically to FPLLs that are especially suitable for use in integrated circuitry. FPLLs are well known in the art as evidenced by U.S. Pat. Nos. 4,072,909; 4,091,410 and 4,755,762, all of which are assigned to the assignee of this application and all of which are incorporated by reference herein. FPLLs are biphase stable and require some mechanism for assuring the proper polarity of demodulated output signal when, for example, they are used in television receiver circuits and the like. In the prior art this has taken the form of determining the polarity of lock up from the FPLL output signal (or other suitable indicator) and inverting the FPLL output signal as required, to assure a desired demodulated output signal polarity.
Difficulty is often experienced in practical FPLL circuits due to small disturbances caused by offsets from stray DC voltages and currents that tend to introduce non linearities into the system. When considering an FPLL implementation in an integrated circuit (IC) environment, any slight offset to the loop can result in unsymmetrical frequency and phase lock characteristics. In addition, these undesirable characteristics may differ between the two different phase lock up modes or conditions.
U.S. Pat. No. 5,745,004, issued to the Applicants and assigned to the present Assignee, produced significant benefits in FPLL design by the simple expedient of relocating the so-called third multiplier from a DC path to an AC path. The DC, or low frequency, path processes the low frequency difference signals that are applied to the loop filter and the voltage controlled oscillator (VCO). The AC path processes the high frequency VCO signals, which in most instances, have high speed edges and are AC coupled. Removal of the third multiplier from the DC path results in more ideal performance due to lower DC offsets and non linearities. In practical implementations, it additionally results in lower power supply voltage requirements. The third multiplier in the AC path performs the function of inverting the 90.degree. phase of the quadrature VCO signal in response to the limiter input. This environment is much more controllable since the waveforms are more uniform in size and tend to be purely digital. Presently a prescaler is used to provide the 0.degree. and 90.degree. phase outputs of the VCO. In this implementation, the third multiplier may conveniently take the form of an exclusive OR gate in the path after the 90.degree. phase shifted VCO output from the prescaler. In general the 0.degree. and 90.degree. phase outputs of the VCO may be produced in other ways and any type of multiplier may be used in this AC path. As those skilled in the art know, care needs to be taken to insure a delay match between the in-phase and quadrature mixer circuits to keep them orthogonal.
The present invention retains the benefits of having the third multiplier in an AC path of the FPLL, but utilizes a more complex switched multiplier as the third multiplier, requires a delay matching element and involves a cascode arrangement of multipliers. These disadvantages are offset by the fact that the I and Q multipliers and the VCO and phase shifting circuits are readily available in an integrated circuit chip, thus saving the manufacturer the cost and need to design a special circuit. While the internal functioning of Applicants' patented circuit and that of the present invention is somewhat different, the end result is identical.